Benutzer:Sauron/db4ce15

Belegung Cyclone 4 db4ce15 Dev Board

A01	Vccio8
A02	SDRam DB8
A03	SDRam CLK
A04	SDRam A12
A05	SDRam A9
A06	SDRam A7
A07	SDRam A5
A08	clk10
A09	40 MHz
A10	SDRam DB0
A11	SDRam DB2
A12	SDRam DB4
A13	SDRam DB6
A14	SDRam dqm
A15	SDRam ncas
A16	Vccio7
B01	SDRam DB9
B02	Gnd
B03	SDRam dqm
B04	SDRam cke
B05	SDRam A11
B06	SDRam A8
B07	SDRam A6
B08	Clk11
B09	Clk9
B10	SDRam DB1
B11	SDRam DB3
B12	SDRam DB5
B13	SDRam DB7
B14	SDRam nwe
B15	Gnd
B16	SDRam nras
C01	IO?
C02	SDRam DB10
C03	J15	35
C04	Vccio8
C05	Gnd
C06	J15	34
C07	Vccio8
C08	SDRam A4
C09	J15	26
C10	Vccio7
C11	J15	22
C12	Gnd
C13	Vccio7
C14	J15	15
C15	SDRam ncs
C16	SDRam BA0
D01	SDRam DB11
D02	IO?
D03	J15	38
D04	VccPLL3
D05	J15	36
D06	J15	31
D07	Gnd
D08	J15	29
D09	J15	23
D10	Gnd
D11	J15	19
D12	J15	17
D13	VccPLL2
D14	J15	13
D15	SDRam BA1
D16	SDRam A10
E01	clk1
E02	Gnd
E03	Vccio1
E04	Gnd
E05	Gnd
E06	J15	33
E07	J15	32
E08	J15	30
E09	J15	25
E10	J15	21
E11	J15	18
E12	Gnd
E13	Gnd
E14	Vccio6
E15	clk4
E16	clk5
F01	SDRam DB13
F02	SDRam DB12
F03	J15	37
F04	Prog.
F05	Vcc
F06	Gnd
F07	Vcc
F08	J15	27
F09	J15	28
F10	Gnd
F11	Vcc
F12	Vcc
F13	J15	14
F14	J15	11
F15	SDRam A0
F16	SDRam A1
G01	SDRam DB15
G02	SDRam DB14
G03	Vccio1
G04	Gnd
G05	J15	40
G06	Vcc
G07	Vcc
G08	Vcc
G09	Vcc
G10	Vcc
G11	J15	60
G12	Prog.
G13	Gnd
G14	Vcc
G15	SDRam A2
G16	SDRam A3
H01	clk?
H02	IO?
H03	JTAG
H04	JTAG
H05	Prog.
H06	Vcc
H07	Gnd
H08	Gnd
H09	Gnd
H10	Gnd
H11	Vcc
H12	Prog.
H13	Prog.
H14	Prog.
H15	Gnd
H16	Gnd
J01	IO?
J02	IO?
J03	Prog.
J04	JTAG
J05	JTAG
J06	Vcc
J07	Gnd
J08	Gnd
J09	Gnd
J10	Gnd
J11	Gnd
J12	J15	7
J13	IO?
J14	J15	8
J15	IO?
J16	J14	4
K01	IO?
K02	IO?
K03	Vcc
K04	Gnd
K05	J16	25
K06	J16	20
K07	Vcc
K08	Gnd
K09	IO?
K10	J15	9
K11	Vcc
K12	J14	13
K13	Gnd
K14	Vcc
K15	J14	3
K16	J14	6
L01	J16	38
L02	J16	36
L03	J16	27
L04	J16	26
L05	Vcc
L06	J16	22
L07	J16	11
L08	J16	21
L09	J14	19
L10	J15	10
L11	IO?
L12	Vcc
L13	J14	16
L14	J14	7
L15	J14	5
L16	J14	8
M01	Clk3
M02	Clk2
M03	Vcc
M04	Gnd
M05	Gnd
M06	J16	16
M07	J16	15
M08	J16	12
M09	J16	8
M10	J16	7
M11	J14	15
M12	Gnd
M13	Gnd
M14	Vcc
M15	Clk6
M16	Clk7
N01	J16	35
N02	J16	34
N03	J16	24
N04	VccPLL1
N05	J16	19
N06	J16	18
N07	Gnd
N08	J16	13
N09	J16	9
N10	Gnd
N11	J16	5
N12	J14	17
N13	VccPLL4
N14	J14	18
N15	J14	9
N16	J14	10
P01	J16	33?
P02	J16	34
P03	J16	25
P04	VccIO3
P05	Gnd
P06	J16	17
P07	VccIo3
P08	J16	14
P09	J16	10
P10	VccIo4
P11	J16	06
P12	Gnd
P13	VccIo4
P14	J14	20
P15	J14	11
P16	J14	12
R01	J16	33?
R02	Gnd
R03	J16	31
R04	IO?
R05	IO?
R06	J14	33
R07	J11	31
R08	Clk15
R09	50 MHz
R10	J14	29
R11	J14	27
R12	J14	25
R13	J14	23
R14	J14	21
R15	Gnd
R16	J14	14
T01	VccIO1
T02	J16	32
T03	J16	30
T04	IO?
T05	IO?
T06	IO?
T07	J14	34
T08	Clk14
T09	Clk12
T10	J14	32
T11	J14	30
T12	J14	28
T13	J14	26
T14	J14	24
T15	J14	22
T16	Vccio4

Belegung J15

01
02
03
04
05
06
07	J12
08	J14
09	K10
10	L10
11	F14
12
13	D14
14	P14 F13
15	C14
16	G11
17	D12
18	E11
19	D11
20
21	E10
22	C11
23	D9
24
25	E9
26	C9
27	F8
28
29	D8
30	E8
31	D6
32	E7
33	E6
34	C6
35	C3
36	D5
37	F3
38	D3
39
40	G5

Belegung J16

01
02
03
04
05	N11
06	P11
07	M10
08	M9
09	N9
10	P9
11	L7
12	M8
13	N8
14	P8
15	M7
16	M6
17	P6
18	N6
19	N5
20	K6
21	L8
22	L6
23
24	N3
25	P3 K5
26	L4
27	L3
28
29
30	T3
31	R3
32	T2
33	???
34	P2 N2 ??
35	N1
36	L2
37
38	L1
39
40