Vortragsprogramm/2011/Aufbau und Nutzung von FPGAs/stoppuhr

`timescale 1ns / 1ps
module test4(clk,button1,button2,button3,button4, ziffer, ziffer_on,dot);

    input clk;
    input button1;
    input button2;
    input button3;
    input button4;
    output [6:0] ziffer;
	 output [0:3] ziffer_on;
	 output reg dot;

	reg [3:0] cnt1 = 0;
	reg [3:0] cnt2 = 0;
	reg [3:0] cnt3 = 0;
	reg [3:0] cnt4 = 0;
	reg [3:0] cnt1_b = 0;
	reg [3:0] cnt2_b = 0;
	reg [3:0] cnt3_b = 0;
	reg [3:0] cnt4_b = 0;
	reg [23:0] t_cnt = 0;
	reg run;
	reg [23:0] dot_cnt = 0;
	reg t_en;
	reg lap_1;
	reg lap_i;
	
	
	wire start_i;
	wire stop_i;
	wire reset_i;
	
//	assign dot = 1'b1;


debounce db1(clk,button1,start_i);
debounce db2(clk,button2,stop_i);
debounce db3(clk,button3,reset_i);
debounce db4(clk,button4,lap);


display d1(clk, cnt4_b, cnt3_b,cnt2_b, cnt1_b, ziffer, ziffer_on);




// run = 1  wenn der Zähler läuft
always @ (posedge clk)
if (start_i == 1) 
	run <=  1'b1;
else if (stop_i == 1) 
	run <= 1'b0;
	
	
	
// alle x Takte einen weiterzählen	
always @ (posedge clk) 
begin

   t_cnt <= t_cnt + 1;
	
	if (t_cnt == 5000000)
	t_cnt <= 0;

if (t_cnt == 0) t_en <= 1;
else t_en <= 0;
end

// Taste Lap
always @ (posedge clk) begin
lap_1 <= lap;
if (!lap_1 && lap)
lap_i <= !lap_i;
end



always @ (posedge clk) begin
 
if (reset_i) begin

cnt1 <= 0;
cnt2 <= 0;
cnt3 <= 0;
cnt4 <= 0;
end
else


// Punkt blinken lassen
dot_cnt <= dot_cnt + 1;
if (ziffer_on == 4'b1101)
dot <= dot_cnt [23] && run;
else
dot <= 1;

// Bei Reset Counter löschen
		if (!lap_i) begin
		cnt1_b <= cnt1;
		cnt2_b <= cnt2;
		cnt3_b <= cnt3;
		cnt4_b <= cnt4;
		end


	if (run && t_en) 
	   begin

	

// 4. Ziffer	
		if (cnt1 == 9) 
			cnt1 <= 0; 
		else
			cnt1 <= cnt1 + 1  ;
			
// 3. Ziffer
		if (cnt1== 9)
			if (cnt2==9) 
				cnt2 <= 0;
			else 
				cnt2 <= cnt2 + 1;

		
// 2. Ziffer
 
		if (cnt2==9 && cnt1 ==9) 

			if (cnt3 == 9) 
				cnt3 <= 0;
			else 
				cnt3 <= cnt3 +1;

		end 
end

		
	
endmodule