SDRT2: Unterschied zwischen den Versionen
Siro (Diskussion | Beiträge) (Die Seite wurde neu angelegt: „{{ProjektInfoBox |name = SDRT2 |status = experimental |image = |description = use the VGA port to transmit I/Q signals on any frequency |aut…“) |
Siro (Diskussion | Beiträge) (Mode description) |
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Hardware to transmit anything on any frequency. That means any information / modulation can be transmited on a channel between 100 and 2400 Mhz, which is the possible internal PLL frequency-range for ADRF6755. The I/Q signals are feed through a VGA-compatible 15pole-DSUB connector. <br> | Hardware to transmit anything on any frequency. That means any information / modulation can be transmited on a channel between 100 and 2400 Mhz, which is the possible internal PLL frequency-range for ADRF6755. The I/Q signals are feed through a VGA-compatible 15pole-DSUB connector. <br> | ||
This board is intended to be used with [[VGAtoBaseband]].<br> | This board is intended to be used with [[VGAtoBaseband]].<br> | ||
While [[SDRT]] was configured using | While [[SDRT]] was configured using a teensy this board is connected to the VGA i2c and can be controlled from any Software that has access to this bus. | ||
The board has a 50Ohms SMA connector transmitting about 0dBm using VGA signals (0.7Vpp). | The board has a 50Ohms SMA connector transmitting about 0dBm using VGA signals (0.7Vpp). | ||
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=== Clock === | === Clock === | ||
26 Mhz TCXO +-2 ppm 1.8V | 26 Mhz TCXO +-2 ppm 1.8V | ||
As there is a frequency error of at least +-2ppm the software has to add an offset to the selected rf frequency. The adrf6755 can be configured in 1Hz steps. The offset has to be measured initialy using precise frequency counters. | |||
=== Low pass === | === Low pass === | ||
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All three channels are terminated using 75 Ohms. | All three channels are terminated using 75 Ohms. | ||
=== SPI == | == Differential opamps == | ||
Opamps are used to generate two differential signal with a common mode voltage of 0.5V. | |||
Each signal is filtered and then feed into the Adrf6755. | |||
=== SPI/I2c == | |||
This board can be configured by internal VGA i2c or by SPI. External pins are connected to SPI signals. Once in SPI mode the board has to be powered to use i2c again. | |||
The SPI interface should have series resistance of more than 50 Ohms. | The SPI interface should have series resistance of more than 50 Ohms. | ||
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* internal LO divider 1:4 | * internal LO divider 1:4 | ||
* fin: 26Mhz ac coupled | * fin: 26Mhz ac coupled | ||
* internal gain control | |||
* lo output freq: | * lo output freq: | ||
fout = fin / 4 * ( INT + (mod / frac) ) | fout = fin / 4 * ( INT + (mod / frac) ) | ||
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== hf Power amplifier == | == hf Power amplifier == | ||
Amplifies the HF signals by about +20 dB. | |||
== Layout == | == Layout == | ||
Version vom 5. Mai 2013, 09:25 Uhr
| SDRT2 Release status: experimental [box doku] | |
|---|---|
| Description | use the VGA port to transmit I/Q signals on any frequency |
| Author(s) | siro (siro) |
| Last Version | 0.1 () |
| License | GPL |
Software Defined Radio Transmitter
Description
Hardware to transmit anything on any frequency. That means any information / modulation can be transmited on a channel between 100 and 2400 Mhz, which is the possible internal PLL frequency-range for ADRF6755. The I/Q signals are feed through a VGA-compatible 15pole-DSUB connector.
This board is intended to be used with VGAtoBaseband.
While SDRT was configured using a teensy this board is connected to the VGA i2c and can be controlled from any Software that has access to this bus.
The board has a 50Ohms SMA connector transmitting about 0dBm using VGA signals (0.7Vpp).
[[Datei:|thumb]]
Board
Overview
- VGA DSUB connector, baseband input
- power jack DC 6 - 7 V > 600mA
- 2 LEDS
- power
- todo
- SMA connector, rf output
- switch (rf disable/enable)
Clock
26 Mhz TCXO +-2 ppm 1.8V As there is a frequency error of at least +-2ppm the software has to add an offset to the selected rf frequency. The adrf6755 can be configured in 1Hz steps. The offset has to be measured initialy using precise frequency counters.
Low pass
The low pass is critical as it phaseshifts the high frequencies. All three channels are terminated using 75 Ohms.
Differential opamps
Opamps are used to generate two differential signal with a common mode voltage of 0.5V. Each signal is filtered and then feed into the Adrf6755.
= SPI/I2c
This board can be configured by internal VGA i2c or by SPI. External pins are connected to SPI signals. Once in SPI mode the board has to be powered to use i2c again. The SPI interface should have series resistance of more than 50 Ohms.
ADRF6755
- reference design
- internal vco and pll is used
- LO path is disabled
- input multiplier 1:1
- internal LO divider 1:4
- fin: 26Mhz ac coupled
- internal gain control
- lo output freq:
fout = fin / 4 * ( INT + (mod / frac) ) where: INT, MOD, FRAC are register values
hf Power amplifier
Amplifies the HF signals by about +20 dB.
Layout
todo